1. Field of Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a dynamic random access memory (DRAM) device with an ultra-short channel and an ultra-shallow junction.
2. Description of Related Art
As the dimensions of a semiconductor device are gradually reduced, the control of the critical dimension in a photolithography process, however, is hindered by the limitations of the light resolution and the depth of focus (DOF). This hindrance seriously affects the pursuit of a reduced memory cell area. Even when using an improved technique, such as phase shift mask (PSM), the photoresist is still unable to provide a reproducible definition.
The conventional approach to reduce the critical dimension usually requires employment of a more complicated mask, for example, PSM, and to conduct a special exposure technique, for example, an off-axial illumination. The purpose of reducing the critical dimension is achieved with the above approach; the manufacturing cost of an integrated circuit, however, is also increased significantly.
Although photolithography is one of the major techniques leading the development of semiconductor devices, it is also a major contributor to the manufacturing cost of the semiconductor. It is therefore desirable to employ less technically demanding photolithography techniques to form a small channel length and a device with a smaller dimension. Both the cost of production and the technical demands can be lowered while the operating speed of the device is improved.
Furthermore, due to the increase of the integration of a DRAM device, the dimensions of the memory cell and the area occupied by the DRAM capacitor are being reduced. Lowering the device dimension, however, lowers the capacitance. For a highly integrated DRAM device, a three dimensional capacitor is needed to maintain its capacitance at an acceptable value. As a result, a stacked capacitor, a trench-stacked capacitor or a crown-shaped capacitor is used to provide a large capacitor area and to lower the interference between the DRAM memory cells. As the complexity of the capacitor structure continues to increase, the height of the capacitor also increases. A capacitance-over-bit (COB) line is therefore normally used for the design of a storage node to avoid the limitation of space in the design of a capacitor.